Synopsys Freshers recruitment drive 2020, Synopsys off campus drive, Freshers jobs in Bangalore , Fresher job openings, freshers jobs, offcampus jobs, jobs for freshers
Synopsys Freshers Recruitment Drive 2020 Hiring For R&D Engineer Position – BE/BTech/ME/MTech | Bangalore
Synopsys Freshers Recruitment Drive 2020 Hiring For R&D Engineer Position – BE/BTech/ME/MTech
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules.
Synopsys Off Campus Fresher Recruitment Details
Company Name: Synopsys
Degree Needed: BE/BTech/ME/MTech
Experience Needed: 0-2 Yrs
Job Profile: R&D Engineer
Work Location: Bangalore
Job Description and Requirements
• We’re looking for a R&D engineer in the ProtoCompiler R&D team in Bangalore for the following role.
• You would be responsible for designing, developing, troubleshooting, debugging and maintaining large and efficient software systems for partitioning, logic, timing optimization, technology mapping steps of the FPGA prototyping software.
You would be expected to:
• Given a requirement or functional specification, design and implement efficient data structures and algorithms in C/C++.
• Work with AE team in test planning, execution and customer support.
• Maintain and support existing product and features.
You will have:
• B.Tech/M. Tech in CS/EE from a reputed institute.
• Sound knowledge in data structures, graph algorithms and C/C++ programming on Windows/Unix.
• Familiarity in digital logic design.
• Familiarity with Verilog/VHDL RTL level designs, timing constraints, static timing analysis
• 0-2 years of experience in designing, developing and maintaining large EDA software.
• Working knowledge of FPGA prototyping tools and flows is a plus.
Apply Before the link Expires
To apply for this job please visit sjobs.brassring.com.